Special Sessions

Title: RISC-V and Open hardware: research, training and innovation towards Open-source Hw/Sw IP Infrastructure development 

Special Session Organizers: 

Francesc Moll, (Universitat Politècnica de Catalunya, Spain) 

Lluís Terés (IMB-CNM , CSIC, Spain) 

Summary

The RISC-V ISA was born in 2010 at UC Berkeley aiming, not just to create a new RISC machine, but an open, advanced, refined and modular instruction set to address the open hardware challenges from the point of view of processor-based developments. RISC-V International came up to guide the open ISA standard independent evolution, and right now thousands of worldwide members from industry and academia are part of the RISC-V ecosystem and many hardware implementations of RISC-V ISA have been made available as open source code ready for its physical materialization either in FPGA or in SoC, as well as components at chip level ready for systems development. The EU Chips Act is betting on open architectures such as RISC-V for its future processors and clearly proposes the EU Design Platform strategy based on open tools, PDKs and IP catalogues.

In the last editions of the DCIS conference there has been a special session devoted to RISC-V and open hardware. This year the special session title remains on its fundamental topic “RISC-V and Open hardware: research, training and innovation …”, but is devoted to “… towards Open-source Hw/Sw IP Infrastructure development” and not only devoted to RISC-V, but addressing any kind of hardware, digital and analogue, aiming to become open. Thus, in this session we aim to open the discussions around all these topics while trying to share results and contribute to European goals and targets. In this sense, we expect contributions on any related topic to have the right picture of the research community in this domain.

Red-RISCV Spanish research network and SOHA (Spanish Open Hardware Association) are contributing to organize this special session.